1. Field of the Invention
The present invention relates to a cryptographic device performing encryption or decryption on input data, and more particularly, to a cryptographic device having a session memory bus for communicating with a session memory.
2. Discussion of Related Art
Increases in information speed, communication speed, and Internet traffic has lead to sudden increases in processing speed and amounts of data, which has resulted in increases in requests for security service. As technology develops and cryptographic algorithms become more complicated, recently developed cryptographic devices increasingly use a dedicated cryptographic processor capable of processing a large amount of computation required for performing a complicated cryptographic algorithm. In addition, the cryptographic devices generally comprise a general-purpose processor, e.g., a Central Processing Unit (CPU), or a processor performing not only encryption/decryption functions but also other functions to support various requirements for an information security system.
FIG. 1 is a block diagram of a conventional cryptographic device.
Referring to FIG. 1, the conventional cryptographic device comprises a CPU 110, a session memory 130, a cryptographic processor 140 and an Input/Output (I/O) interface 150 connected via one common data bus. The right to use the data bus is managed by a Direct Memory Access (DMA) bus master 120.
The session memory 130 storing an encrypt key, a decrypt key, an Initial Vector (IV), Initial Data (ID), etc., is frequently accessed by the CPU 110 upon session initialization or close, and also is frequently accessed by the cryptographic processor 140 during an encryption or decryption process.
While the CPU 110 or the I/O interface 150 uses the data bus for an operation other than access to the session memory 130, the cryptographic processor 140 may frequently require access to the session memory 130 during an encryption or decryption process. In this case, although the session memory 130 is not accessed by a device, the cryptographic processor 140 cannot access the session memory 130 because only one device can use the common data bus. In other words, the cryptographic processor 140 can access the session memory 130 after the CPU 110 or the I/O interface 150 finishes its operation. Therefore, the overall performance of the conventional cryptographic device deteriorates due to delay time caused while the cryptographic processor 140 accesses the session memory 130.